The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) and, more particularly, to an improvement of its read rate.
A semiconductor memory device represented by a DRAM has a memory cell array in which a plurality of memory cells are arranged in a matrix. Each memory cell is arranged at the intersection between a word line and a bit line. When a word line and a bit line are selected on the basis of a row address and a column address, a specific memory cell is accessed.
In a semiconductor memory device with such an arrangement, the read time for a column address is shorter than that for a row address. More specifically, in the read for a row address, a word line is selected in accordance with the row address, and data in a plurality of memory cells connected to this word line are read out to a corresponding bit line. For this reason, the read time is long. To the contrary, in the read for a column address, when the row address is determined, data in memory cells connected to this word line have already been read out to the bit line, as described above. For this reason, for the column system, data can be read out by only selecting a bit line, so the read time can be made shorter than that for the row system.
As a DRAM whose data transfer rate is improved by paying attention to the above characteristics, for example, an SDRAM (Synchronous DRAM) is known. In a high-speed DRAM of this type, the data transfer rate is increased by improving the read rate for the column system.
A conventional semiconductor memory device will be described in detail while exemplifying an SDRAM having a bank A and a bank B. FIG. 20 shows the arrangement of one bank of the SDRAM. Memory cell arrays 10A and 10B are formed by arraying, in a matrix, memory cells M each having a data storage capacitor and a cell transistor. In the memory cell arrays 10A and 10B, word lines WL and pairs of bit lines BL and bBL (b represents an inverted signal) extend in the row and column directions, respectively. The memory cells M on one word line WL are formed on one side of the bit line BL or bBL.
Each pair of bit lines BL and bBL of the memory cell arrays 10A and 10B is connected to a sense amplifier 50 through a pair of transistors 30a and 30b and a pair of transistors 31a and 31b. The sense amplifier 50 is shared by the memory cell arrays 10A and 10B. A row decoder 20J selects a word line WL of the memory cell array 10A on the basis of an external row address. The memory cell array 10B also has a row decoder (not shown).
FIG. 20 shows only one pair of bit lines BL and bBL. However, the memory cell arrays 10A and 10B have a plurality of pairs of bit lines BL and bBL. The pair of transistors 30a and 30b and the pair of transistors 31a and 31b are arranged in correspondence with each bit line pair. FIG. 20 shows the arrangement of, e.g., the bank A. The bank B (not shown) also has the same arrangement as that of the bank A.
The read operation of the SDRAM having the bank A and bank B (not shown) will be described below with reference to the timing chart shown in FIG. 21. The burst length is, e.g., "4", and the CAS (Column Address Strobe) latency is, e.g., "2".
To access the bank A to read out data, an activate command "Act" for activating the bank A is executed to operate the row system of the bank A (activation of bank A). More specifically, the word line WL of the bank A, which is designated by a row address Ra, is set at a high level to output data from the memory cells M connected to this word line WL to the pair of bit lines BL and bBL.
Next, a read command "Read" is executed to operate the column system of the bank A. More specifically, a pair of bit lines BL and bBL designated by a column address Ca is selected to read out data output to this bit line pair. Since the CAS latency is "2", data Aa0 to Aa3 with a burst length of 4 are continuously read out two clocks after execution of the read command.
During the data read from the bank A, the bank B is activated. For this reason, data Bb0 to Bb3 are sequentially read out from the bank B continuously following the data Aa0 to Aa3 from the bank A. At this time, the activation time of the bank B overlaps the read access to the bank A. Hence, the read access to the bank B is apparently performed at a high speed.
After this, when the row address is changed from "Rb" to "Rc" to access the bank B again, data necessary for the read have not been transferred to the sense amplifier yet (this is called a miss hit). First, a precharge command "PRE" is executed to precharge the main portions of the bank B to erase remaining data. After this, the activate command is executed to set a word line designated by the row address Rc at high level, and then, the read command is executed to sequentially read out data Bc0 to Bc3. In this case, a period Tb without data output is present between the data Bb0 to Bb3 and data Bc0 to Bc3, and the time required for precharge or activation becomes conspicuous.
As described above, according to the conventional semiconductor memory device, in a miss hit due to a change in row address, the time required for precharge or activation becomes conspicuous to lower the read rate.